The present invention relates to a method for forming high aspect ratio metal lines of a semiconductor device.
A more densely integrated semiconductor device needs high aspect ratio metal lines having narrower gaps filled with a dielectric substance. The narrow gaps, however, are difficult to fill and therefore can lead to unwanted voids and discontinuities in an insulating or gap-fill material.
FIGS. 1A to 1C illustrate a sequential flow of a conventional process for forming metal lines of high aspect ratio. In FIG. 1A, after a metal layer 1 is prepared on a semiconductor substrate 10, photolithography is performed to form a photoresist pattern 2 on the metal layer 1, which is partially exposed therethrough. Reactive ion etching (RIE) is applied to the metal layer 1 by using the photoresist pattern 2 as a mask and, then, the photoresist pattern 2 in FIG. 1A is removed to form a plurality of metal lines 11 as shown in FIG. 1B, wherein a gap is interposed between adjacent metal lines 11. In FIG. 1C, high density plasma (HDP) is used to form an inter-metal dielectric (IMD) 12 that fills the gaps interposed between the adjacent metal lines 11.
If the metal lines 11 have high aspect ratios, inter-metal dielectric 12 is bridged or pinches off before the gap is completely filled from the bottom thereof. As a result, voids 13 in FIG. 1C may be formed in the inter-metal dielectric 12 and cause serious reliability problems because of the potential for trapped contamination. Further, if an etch rate is increased during the HDP process to keep the gaps open longer for the purpose of preventing the formation of metal bridges in the gaps, corner clippings 14 may be formed on a top portion of the metal lines 11. These corner clippings 14 also represent a potential reliability issue.
It is, therefore, an object of the present invention to provide an improved method of forming high aspect ratio metal lines without voids and corner clippings.
In accordance with the preferred embodiment of the invention, there is provided a method for forming metal lines of a semiconductor device, the method including the steps of: forming a first metal layer on a substrate; patterning the first metal layer to form a plurality of first metal lines spaced apart from each other with a gap interposed between adjacent first metal lines; forming a first dielectric layer to fill the gaps interposed among the first metal lines; planarizing the first dielectric layer such that top surfaces of the first metal lines are exposed; forming a second metal layer on the first dielectric layer and the first metal lines; patterning the second metal layer to form a plurality of second metal lines being positioned on the plurality of first metal lines, respectively, wherein each of the first metal lines and a corresponding second metal line form an integral metal line; and forming a second dielectric layer to fill gaps interposed among the second metal lines, wherein the first dielectric layer and the second dielectric layer form an integral dielectric layer that fills gaps interposed among the integral metal lines.